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Wafer-Level Testing and Test During Burn-in for Integrated Circuits by Krishnendu Chakrabarty and Sudarshan Bahukudumbi (2010, Hardcover)

About this product

About this product

Product Information

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Identifiers

Publisher
Artech House
ISBN-10
1596939893
ISBN-13
9781596939899
eBay Product ID (ePID)
78670426

Product Key Features

Author
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Publication Name
Wafer-Level Testing and Test During Burn-In for Integrated Circuits
Format
Hardcover
Language
English
Publication Year
2010
Type
Textbook
Number of Pages
215 Pages

Additional Product Features

Lc Classification Number
Tk7874.B35 2010
Copyright Date
2010
Target Audience
Scholarly & Professional
Topic
Electronics / Semiconductors, Electronics / Circuits / Integrated
Lccn
2010-455090
Dewey Decimal
621.3815/48
Dewey Edition
22
Illustrated
Yes
Genre
Technology & Engineering

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